1) Field of the Invention
The present invention relates to the field of semiconductor fabrication and more particularly to metal-oxide-semiconductor (MOS) fabrication and to a process for preventing the formation of precipitates on a substrate surface after a contact layer is subjected to an etch back step.
2) Description of the Prior Art
In the manufacture of semiconductor devices, it is normally necessary to make electrical contact to device regions on the substrate surface through an overlying dielectric layer. This is accomplished by first forming an opening or via (contact via) in the dielectric layer over the region to be electrically contacted, and next filling the contact via with a conductive material.
In addition to filling the vias with a conductive material, it is necessary to electrically connect certain device regions with others, as well as to provide for electrical connection to external leads. These requirements are met by forming a wiring layer on the surface of the substrate. The wiring layers are formed by depositing a conductive material on top of the dielectric layer in which vias have been formed. The conductive layer is then masked and etched to leave continuous lines of conducive material necessary to match the appropriate connections to the device regions of the substrate. These lines are known as interconnects.
Several conductive materials can be used as contact via fill. In larger geometry devices, the via fill and interconnect are formed simultaneously using one conductive layer. For example, aluminum (Al) can be deposited on the entire substrate, as well as in the vias in one deposition step. The areas over the vias and interconnects are then masked with photoresist and the aluminum is etched from the exposed remaining areas, leaving the vias filled with aluminum as well as forming interconnect lines on the surface of the dielectric layer.
As device geometries have shrunk to submicron levels and devices have become more densely packed on the substrate surface, the aspect ratio (ratio of height to width) of the vias to the device regions has greatly increased. Using one aluminum deposition step to form both the via contacts (plug) and interconnect lines has proven to be inadequate in devices with high aspect ratios. Problems encountered include poor step coverage, poor contact integrity, and inadequate polarity. To overcome these shortcomings, tungsten and other refractory metals are being used as a contact filling (plugs) for devices with submicron contacts before aluminum deposition and patterning. For example, a blanket tungsten (W) is deposited. Next, a blanket etch back removes the deposited tungsten from the substrate surface, leaving a tungsten (W) filling or plug in the contact openings. The tungsten layer is etched back in a plasma etcher, such as in a LAM Research Equipment etcher model 4720. An aluminum layer is then deposited, covering the substrate surface including the filled contact vias. This aluminum film is then patterned and etched to form the interconnects lines between devices.
To improve the reliability of the interconnects and contacts, it has become a widely accepted practice to deposit a barrier metal layer such as TiN, TiW or the like within the contact hole and in surrounding areas. The barrier layer is formed over the dielectric layer and under the plug (e.g., W) and the interconnect layer (e.g., Al). The barrier layer can be formed by a sputter process. This barrier layer prevents undesirable reactions between the substrate material (e.g., Si) and the wiring material or between the dielectric layer (e.g., silicon oxide) or polysilicon and the wiring material (e.g., aluminum).
A problem with the current process of etching back a contact layer that is formed over a barrier layer containing titanium is that a precipitate often forms on the barrier layer. This precipitate, often violet in color, can cause circuit failure by interfering with the metal and insulation layer formed over the TiN and precipitate. The precipitate often appears to form a brown ring around the outside edge of the wafer. This precipitate can cause circuit failure by interfering with the metal and insulation layer formed over the precipitate and the barrier layer. Also, the precipitate can cause reliability problems, such as electro migration, metal peeling, and metal bridging. Many solutions have been tried without satisfactory success to eliminate this precipitation problem.
Therefore, there is a need for a process to remove or prevent the formation of precipitates after tungsten etch back. This process optimally should be simple, fast, and inexpensive to implement. It should also not reduce wafer throughput, especially on the etcher.
Davis, U.S. Pat. No. 5,164,330 teaches tungsten etch back process for tungsten layers using a NF.sub.3 /Ar chemistry with three etch steps. This process reduces the amount of residue buildup in the etching reactor.
Kadomura, U.S. Pat. No. 5,227,337 discloses a two step tungsten etch back process where the first step uses S.sub.2 F.sub.2 gas at the high temperature and S.sub.2 F.sub.2 /H.sub.2 at a low temperature.
Petro et al. U.S. Pat. No. 5,326,723 teaches a method of cleaning a CVD process chamber used to deposit tungsten. The chamber undergoes an in-situ cleaning process with NF.sub.3 and H.sub.2 N.sub.2 plasmas.
Sumi, U.S. Pat. No. 5,254,498 discloses a method of forming a barrier metal structure in a contact hole to ensure good metal coverage by the metal. The invention forms an oxide layer over a metal barrier layer (e.g., W) in a contact hole and forming a contact metal over the oxide.
Woo, U.S. Pat. No. 4,833,099 teaches a N.sub.2 anneal after a tungsten deposition but before forming an oxidation layer over the tungsten layer. The N.sub.2 anneal inhibits the tungsten from reacting with oxygen in the oxidation step and allows formation of a planar and uncontaminated oxide layer.